The fabrication of integrated chips can be broadly separated into two main sections, front-end-of-the-line (FEOL) fabrication and back-end-of-the-line (BEOL) fabrication. FEOL fabrication includes the formation of devices (e.g., transistors, capacitors, resistors, etc.) on a semiconductor substrate. BEOL fabrication includes the formation of one or more metal interconnect layers within one or more insulating dielectric layers disposed above the semiconductor substrate. The metal interconnect layers of the BEOL electrically connect individual devices of the FEOL to external pins of an integrated chip.
As features of semiconductor devices are reduced, low dielectric constant (LK) materials and extra-low k (ELK) materials that have dielectric constants less than that of silicon dioxide have begun to be implemented in some designs as insulating materials between interconnects. This poses further integration challenges to manufacturers, since the reduction of the dielectric constant is usually achieved at the expense of useful material properties that are required for interconnect fabrication. Therefore, there is a need for improved interconnect fabrication methods, which resolve certain challenges faced by the semiconductor industry.